1. Field of the Invention
The present invention relates to a delay failure test circuit that detects a delay failure between clock domains in a tested circuit such as large scale integration (LSI).
2. Description of the Related Art
Recently, it has become increasingly important in shipment tests of LSI to detect a delay failure in addition to a stuck-at failure. To improve a detection rate of the delay failure, it is important to detect the delay failure between clock domains.
If a pattern for detecting a delay failure is generated in a conventional test pattern generating technology, first, a capture clock and a clock on the launch side are analyzed in a tested circuit. If the clocks on the launch side and the capture side are the same clocks, the test pattern can be easily generated. If the clocks on the launch side and the capture side are different, it is difficult to generate the test pattern because timing of the clocks must be considered.
FIG. 1 is a circuit diagram of LSI including a conventional delay failure test circuit. In FIG. 1, LSI 1100 is a tested circuit that includes plural clock domains CD (CD1 to CD3 in the example shown in FIG. 1) and a delay failure test circuit 1101 that detects delay failures of the clock domains CD (CD1 to CD3).
The delay failure test circuit 1101 includes a clock source CLK, a reset input terminal R, and a scan mode input terminal SM. Frequency dividing circuits div1 to div3 and selectors 1111 to 1113 are also included for the clock domains CD1 to CD3, respectively. As shown in FIG. 1, the same characters are added to input/output terminals and signals input/output to/from the input/output terminals.
A clock signal CLK is input to each of the frequency dividing circuits div1 to div3 and to each of the selectors 1111 to 1113. A reset signal R is inverted and input to each of the frequency dividing circuits div1 to div3. A scan mode signal SM is input to each of the selectors 1111 to 1113.
Each of the frequency dividing circuits div1 to div3 divides the incoming clock signal CLK. As shown in FIG. 2, when the clock signal CLK is a reference clock signal, the clock signal CLK is divided into N frequency-divided clocks (N is a real number). For example, the frequency dividing circuit div1 divides the clock signal CLK to generate ⅛ frequency and outputs a frequency-divided clock signal CLK1 (=⅛ CLK).
The frequency dividing circuit div2 divides the clock signal CLK to generate ¼ frequency and outputs a frequency-divided clock signal CLK2 (=¼ CLK). The frequency dividing circuit div3 divides the clock signal CLK to generate ½ frequency and outputs a frequency-divided clock signal CLK3 (=½ CLK).
At the subsequent stage to the frequency dividing circuits div1 to div3, the selectors 1111 to 1113 are connected respectively. The frequency-divided clock signals CLK1 to CLK3 are input from the frequency dividing circuits div1 to div3 at the preceding stage to the selectors 1111 to 1113, respectively. The clock signal CLK is also input to each of the selectors 1111 to 1113. Each of the selectors 1111 to 1113 selects an output clock signal based on the scan mode signal SM.
Specifically, if the scan mode signal SM is input, each of the selectors 1111 to 1113 outputs the clock signal CLK. On the other hand, if the scan mode signal SM is not input, the selectors 1111 to 1113 outputs the frequency-divided clock signals CLK1 to CLK3 from the frequency dividing circuits div1 to div3 at the preceding stage, respectively.
At the subsequent stage to the selectors 1111 to 1113, the clock domains CD1 to CD3 are connected via clock buffers 1121 to 1123 respectively. In other words, the frequency-divided clock signals CLK1 to CLK3 output from the selectors 1111 to 1113 are input to the clock domains CD1 to CD3 via the clock buffers 1121 to 1123, respectively.
In such LSI 1100, the following three types of data transfer are possible:
(1) data transfer between the clock domains CD1 and CD2 (an arrow A of FIG. 1);
(2) data transfer between the clock domains CD2 and CD3 (an arrow B of FIG. 1); and
(3) data transfer between the clock domains CD1 and CD3 (an arrow C of FIG. 1).
To detect a delay failure in the LSI 1100, two edges, i.e., launch/capture edges must be put in a one-on-one relationship. The launch edge is a clock serving as timing of outputting data and the capture edge is a clock serving as timing of capturing the output data.
FIG. 2 is a timing chart of the clock signal CLK and the frequency-divided clock signals CLK1 to CLK3 at the time of the failure detection of the LSI 1100. With regard to the data transfer from the clock domain CD3 to the clock domain CD1, the clock must be switched from the frequency-divided clock signal CLK3 to the frequency-divided clock signal CLK1 to achieve the data transfer.
Specifically, until a clock of a second cycle ((2) of CLK1) is input for the frequency-divided clock signal CLK1, clocks of four cycles ((1) to (4) of CLK3) are input for the frequency-divided clock signal CLK3.
That is, since four launch edges ((1) to (4) of CLK3) exist corresponding to one capture edge ((2) of CLK1) in this case, the launch edges and the capture edge are not put in the one-on-one corresponding relationship.
Therefore, for example, a test pattern for detecting a delay failure cannot be generated if data launched at the clock ((4) of CLK3) of the fourth cycle of the frequency-divided clock signal CLK3 are captured at the capture edge ((2) of CLK1) of the frequency-divided clock signal CLK1 (“a” in FIG. 2).
On the other hand, with regard to the data transfer from the clock domain CD1 to the clock domain CD3, the clock must be switched from the frequency-divided clock signal CLK1 to the frequency-divided clock signal CLK3 to achieve the data transfer.
As is the case with the above description, capture edges ((2) to (7) of CLK3) are generated in the frequency-divided clock signal CLK3 corresponding to the launch edge ((1) of CLK1) of the frequency-divided clock signal CLK1. Therefore, a delay failure cannot be detected at a position actually desired (e.g., “b” in FIG. 2).
To eliminate this problem, a delay failure test circuit is suggested which aligns rising edges of plural clock domains (e.g., Published Japanese Translation of PCT Application No. 2004-538466).
However, according to the conventional technology of Published Japanese Translation of PCT Application No. 2004-538466, an influence of signal change among plural first pulses (e.g., an influence of a signal change between a first pulse of clkout(1) and a first pulse of clkout(0) or lastclkout) must be considered at the time of the generation of the test pattern. Therefore, since plural clocks are operated at the same time, all circuits become targets of the test and the generation of the test pattern becomes complicated.